The desire by mission planners to implement viable space communication infrastructures that can facilitate the deployment of next-generation space-based networks creates numerous design challenges for today's spacecraft system engineers. These design challenges are compounded by increasingly demanding space applications and increased mission requirements, and also significant pressure to minimize the overall system costs. Generally, the trend is to implement less costly space communication systems while striving to transport more data to and from user applications. In this regard, a major problem encountered by system designers is that the existing space system architectures and associated design approaches fall short in meeting all of the new design and cost requirements being imposed. Therefore, a new space system architecture and design approach are needed that can provide an optimal balance in meeting existing and future space system design and mission requirements, especially in terms of cost, performance, reliability, flexibility, power consumption and weight.
A current trend in the space industry is towards a modular commercial off-the-shelf design approach. However, the use of off-the-shelf components (e.g., for payload processors, mission specific sensors, communication subsystems, etc.) from numerous different vendors creates a significant interface design problem that has not yet been adequately addressed. For example, the use of different interfaces between the vendors' components reduces the overall flexibility of the systems involved, and leads to increased non-recurring engineering costs (in terms of financial expenses, power consumption and weight). Also, this approach presents a significant design challenge due to rapidly changing standards, the scarcity of space-worthy off-the-shelf interface components, and the basic inflexibility of the network solutions that are available today. In this regard, refer to FIG. 1, which depicts a typical spacecraft system architecture for scientific applications that illustrates the above-described interface problems with the current off-the-shelf design approach.
FIG. 1 depicts a block diagram of a typical architecture for a state-of-the-art spacecraft system 100 using a conventional commercial off-the-shelf design approach, which includes a sensor suite (SS) subsystem 102, a payload data processor (PDP) subsystem 104, and a spacecraft control processor (SCP) subsystem 106. The SS subsystem 102 includes a plurality of sensors 108a-108d, the PDP subsystem 104 includes a plurality of payload data processors 110a-110c, and the SCP subsystem 106 includes a plurality of spacecraft control processors 112a-112c. As illustrated by this example architecture, the current design approach is to use standard point-to-point interfaces between the components of the SS subsystem 102 and PDP subsystem 104. Thus, interfaces 114a-114d are implemented as standard point-to-point interfaces using IEEE 1394 and 1355 high-speed serial links. Additionally, payload data processors 110a-110c in PDP subsystem 104 are implemented as commercial off-the-shelf computer processors, which are interconnected by a standard Compact Peripheral Component Interconnect (cPCI) backplane bus 116. Note that, as illustrated by this example architecture, a conventional solution for a typical SS-PDP interface is to implement one interface per sensor-computer pair.
Spacecraft system 100 depicted in FIG. 1 also includes two major interfaces 118, 120 that interconnect the PDP and SCP subsystems 104, 106. For this example, interface 120 is implemented with an IEEE 1394 serial link between SCP processor 112a and PDP processor 110c so as to exchange control information. Alternatively, interface 120 may be implemented with an IEEE 1355 serial link. Control information is also exchanged between processors 112a and 112b in SCP subsystem 106 using an IEEE 1394 serial link 122. Interface 118 provides data downlink, uplink, and cross-link transmission capabilities using a standard network communication protocol (e.g., ATM). At this point, it is important to note that all of the above-described system interconnects are defined early on in the design cycle, and that specific design remains fixed and inflexible throughout the life of the system involved. Consequently, such design inflexibility severely restricts a user's ability to redistribute data during missions, and also limits the types of applications that can be implemented.
In the types of systems illustrated by FIG. 1, software (rather than hardware) is used for management of the various protocols used. However, implementing such a software/hardware tradeoff leads to additional software development costs and an overall loss of computing power. Thus, there is a pressing need to develop a flexible network infrastructure that can facilitate the interconnection of system components using disparate interface standards, without also incurring an increase in processing overhead, design costs, and/or project risk.
Another problem that exists in this field is that significant advances in chip technologies and wire speeds in the commercial sector are driving a need for faster packet-processing devices, and protocols have become diversified to a great extent. However, two basic design philosophies have evolved to solve this problem. One approach emphasizes increased design flexibility, and the other emphasizes increased processing speed. For example, one such design approach is to use a “general purpose process” to handle network traffic in order to increase flexibility, but this increase comes at the expense of speed. A second approach uses Application-Specific Integrated Circuits (ASICs) for network traffic processing functions in order to increase speed, but this increase comes at the expense of flexibility.
Ultimately, the significant increases in link speeds make “wire speed” processing unattainable with today's “general purpose processor” solutions. Also, the fixed nature of ASICs makes them too inflexible for many applications. However, vendors of processing system components (e.g., routing switches, edge switches, network interface cards, etc.) now realize that it is not enough to simply optimize their products for either flexibility or speed alone, because unless their products can provide the best features of both approaches, they will be incapable of meeting future market demands. Therefore, in order to meet these and other similar challenges, certain designers have been working to develop network devices (the field of “Network Processors”) that should merge the best features of both flexibility and speed.
Nevertheless, although the developers of today's Network Processor designs have achieved some successes in solving certain flexibility versus speed optimization problems, there are still a number of significant problems to be resolved. For example, the existing Network Processor architectures rely on a conventional technique of merging a “general purpose processor” with relatively costly non-programmable ASICs. However, improvements in reconfigurable computing techniques using field-programmable gate arrays (FPGAs) offer additional flexibility for future Network Processor architectures, by providing a custom-made hardware solution that can be reconfigured and adapted for future in-space mission needs. Notwithstanding such improvements, a major drawback of this approach is that there is an inherent flaw in the design of FPGAs that significantly limits the amount of flexibility that can be obtained. For example, today's FPGA devices are composed of a large number of tightly-coupled, fine-grained programmable resources. However, the tightly-coupled nature of the programmable fabric of these FPGAs makes them fall far short of the goal of implementing all of the concepts of the reconfigurable computing paradigm, because the current FPGA designs are not scalable for implementing coarse-grained applications (e.g., in terms of physical interconnections and design engineer effort). Therefore, it would be advantageous to provide a network architecture that can be used, for example, for space-based applications, which efficiently integrates all of the elements required by the reconfigurable computing paradigm and provides an optimal balance between flexibility and speed. As described in detail below, the present invention provides a novel reconfigurable network that can be implemented on a chip, which resolves the above-described interface design problems and other related problems.